ARM Instructions
1145 instructions - showing 100 per page, page 3 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| dmb | DMB <option> | System | Base | Ensures memory access ordering. |
| dmb | DMB <option> | Thumb System | A32 (Base) | Memory barrier (Thumb). |
| dmb | DMB <option> | System | A32 (Base) | Ensures memory access ordering. |
| drps | DRPS | System | System | Restores state from SPSR_ELx and DLR_EL0. |
| dsb | DSB <option> | System | Base | Ensures completion of memory accesses. |
| dsb | DSB <option> | Thumb System | A32 (Base) | Sync barrier (Thumb). |
| dsb | DSB <option> | System | A32 (Base) | Ensures completion of memory accesses. |
| dup | DUP <Vd>.<T>, <R><n> | SIMD Copy | NEON (SIMD) | Duplicates a general-purpose register to all vector elements. |
| dup | DUP <Vd>.<T>, <Vn>.<Ts>[<index>] | SIMD Copy | NEON (SIMD) | Duplicates a vector element to all elements in destination. |
| dup | DUP <Zd>.<T>, <R><n|m> | SVE Move | SVE | Broadcasts a scalar register or immediate to all active vector elements. |
| eon | EON <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | XORs register with NOT of shifted register (XNOR). |
| eon | EON <Xd>, <Xn>, <Xm> {, <shift> #<amount>} | Logical (Register) | Base | XORs 64-bit register with NOT of shifted register. |
| eor | EOR <Wd|Wsp>, <Wn>, #<imm> | Logical (Immediate) | Base | XORs register with immediate. |
| eor | EOR <Wd>, <Wn>, <Wm> {, <shift> #<amount>} | Logical (Register) | Base | XORs two registers. |
| eor | EOR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Bitwise XOR of two vectors. |
| eor | EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE Logic | SVE | Bitwise XOR of two vectors under predicate. |
| eor | EOR{S}<c> <Rd>, <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Performs bitwise XOR. |
| eor.w | EOR.W <Rd>, <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit XOR. |
| eorv | EORV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | XORs all active elements into a scalar. |
| eret | ERET | System | Base | Returns from an exception. |
| eret | ERET | System | A32 (System) | Returns from an exception (A32). |
| eret | ERET | Thumb System | A32 (System) | Returns from an exception (Thumb state). |
| esb | ESB | System Hint | A32 (RAS) | Synchronizes system errors (v8.2). |
| esb | ESB | System Alias | RAS (Reliability) | Synchronizes unrecoverable system errors. |
| ext | EXT <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm> | SVE Permute | SVE | Extracts a vector from a pair (sliding window) using immediate byte index. |
| ext | EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index> | SIMD Extract | NEON (SIMD) | Extracts a vector from a pair of vectors (Sliding window). |
| extr | EXTR <Wd>, <Wn>, <Wm>, #<lsb> | Data Processing | Base | Extracts a register from a pair of registers. |
| extr | EXTR <Xd>, <Xn>, <Xm>, #<lsb> | Data Processing | Base | Extracts a 64-bit register from a pair. |
| fabs | FABS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE FP Unary | SVE | Calculates absolute value of floats. |
| fabs | FABS <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Data Processing | Floating Point | Calculates the absolute value of a float. |
| fabs | FABS <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Calculates absolute value for each element. |
| fabs | FABS <Vd>.8H, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Absolute value of half-precision vector. |
| fadd | FADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Adds two floating-point values. |
| fadd | FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds elements of two floating-point vectors. |
| fadd | FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Adds floating-point elements under predicate. |
| fadd | FADD <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Adds two half-precision floating-point vectors. |
| fadd | FADD <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Adds two single-precision floating-point registers. |
| fadd | FADD <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Adds two double-precision floating-point registers. |
| faddp | FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Adds adjacent pairs of float elements. |
| faddv | FADDV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Sums all active floating-point elements into a scalar result. |
| fcadd | FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE | Performs complex addition with rotation. |
| fcadd | FCADD <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | FEAT_FCMA | Complex addition with rotation (NEON). |
| fccmp | FCCMP <Hn|Sn|Dn>, <Hm|Sm|Dm>, #<nzcv>, <cond> | FP Compare | Floating Point | Compares floats only if condition is met, else sets flags to immediate. |
| fcmeq | FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE | Sets predicate bits where float elements are equal. |
| fcmgt | FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE FP Compare | SVE | Sets predicate bits where float Zn > Zm. |
| fcmla | FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, #<rot> | SVE FP Complex | SVE | Performs complex multiply-accumulate. |
| fcmla | FCMLA <Vd>.4S, <Vn>.4S, <Vm>.4S, #<rot> | NEON Complex | FEAT_FCMA | Complex multiply-accumulate with rotation (NEON). |
| fcmp | FCMP <Hn|Sn|Dn>, <Hm|Sm|Dm|#0.0> | FP Compare | Floating Point | Compares two floating-point values and updates process flags (NZCV). |
| fcmp | FCMP <Sn>, <Sm> | Float Compare | F.P. | Compares two single-precision registers and updates NZCV flags. |
| fcmp | FCMP <Dn>, <Dm> | Float Compare | F.P. | Compares two double-precision registers and updates NZCV flags. |
| fcsel | FCSEL <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <cond> | FP Data Processing | Floating Point | Selects one of two floats based on condition flags. |
| fcvt | FCVT <Hd|Sd|Dd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts between float precisions (e.g., Half <-> Single <-> Double). |
| fcvtas | FCVTAS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding to nearest. |
| fcvtau | FCVTAU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding to nearest. |
| fcvtl | FCVTL <Vd>.4S, <Vn>.4H | NEON FP16 | FEAT_FP16 (NEON) | Converts Half-precision (Bottom) to Single-precision. |
| fcvtl | FCVTL <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | NEON (SIMD) | Converts narrow floats to wide floats (e.g., Half -> Single). |
| fcvtl2 | FCVTL2 <Vd>.4S, <Vn>.8H | NEON FP16 | FEAT_FP16 (NEON) | Converts Half-precision (Top) to Single-precision. |
| fcvtms | FCVTMS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding towards minus infinity (Floor). |
| fcvtmu | FCVTMU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards minus infinity. |
| fcvtn | FCVTN <Vd>.4H, <Vn>.4S | NEON FP16 | FEAT_FP16 (NEON) | Converts Single-precision to Half-precision (Bottom). |
| fcvtn | FCVTN <Vd>.<Td>, <Vn>.<Ts> | SIMD Two Register | NEON (SIMD) | Converts wide floats to narrow floats (e.g., Single -> Half). |
| fcvtn2 | FCVTN2 <Vd>.8H, <Vn>.4S | NEON FP16 | FEAT_FP16 (NEON) | Converts Single-precision to Half-precision (Top). |
| fcvtns | FCVTNS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding to nearest (bankers' round). |
| fcvtnu | FCVTNU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding to nearest (bankers' round). |
| fcvtps | FCVTPS <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to signed integer, rounding towards plus infinity (Ceil). |
| fcvtpu | FCVTPU <Wd|Xd>, <Hn|Sn|Dn> | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards plus infinity. |
| fcvtzs | FCVTZS <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts floats to signed integers (Truncate). |
| fcvtzs | FCVTZS <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating Point | Converts float to signed integer, rounding towards zero (Truncate). |
| fcvtzs | FCVTZS <Xd>, <Dn> | Float Conversion | F.P. | Converts floating-point to signed integer. |
| fcvtzs | FCVTZS <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | NEON (SIMD) | Converts floats to signed integers (Truncate). |
| fcvtzu | FCVTZU <Zdn>.<T>, <Pg>/M, <Zdn>.<T> | SVE Conversion | SVE | Converts floats to unsigned integers (Truncate). |
| fcvtzu | FCVTZU <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>} | FP Conversion | Floating Point | Converts float to unsigned integer, rounding towards zero (Truncate). |
| fcvtzu | FCVTZU <Vd>.<T>, <Vn>.<T> {, #<fbits>} | SIMD Two Register | NEON (SIMD) | Converts floats to unsigned integers (Truncate). |
| fdiv | FDIV <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Divides two floating-point values. |
| fdiv | FDIV <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Divides elements of floating-point vectors. |
| fdiv | FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Divides floating-point elements under predicate. |
| fdiv | FDIV <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Divides two half-precision floating-point vectors. |
| fdiv | FDIV <Sd>, <Sn>, <Sm> | Float Data Proc | F.P. | Divides two single-precision floating-point registers. |
| fdiv | FDIV <Dd>, <Dn>, <Dm> | Float Data Proc | F.P. | Divides two double-precision floating-point registers. |
| fjcvtzs | FJCVTZS <Wd>, <Dn> | Float Convert | FEAT_JSCVT | Converts double to signed 32-bit integer with JS rounding semantics. |
| fmadd | FMADD <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm>, <Ha|Sa|Da> | FP Data Processing | Floating Point | Calculates (Vn * Vm) + Va without intermediate rounding. |
| fmax | FMAX <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns the larger of two values. |
| fmax | FMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares and returns the larger value per element. |
| fmax | FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Determines maximum value of active float elements. |
| fmax | FMAX <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Finds max of half-precision vectors. |
| fmaxnm | FMAXNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns larger value, handling NaNs according to IEEE 754-2008 'maxNum'. |
| fmaxp | FMAXP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Max of adjacent float elements. |
| fmaxv | FMAXV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds max float in vector. |
| fmaxv | FMAXV <Sd>, <Vn>.<T> | NEON Reduction | NEON (v8.0) | Finds max float in a vector. |
| fmin | FMIN <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns the smaller of two values. |
| fmin | FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares and returns the smaller value per element. |
| fmin | FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> | SVE FP Binary | SVE | Determines minimum value of active float elements. |
| fmin | FMIN <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Finds min of half-precision vectors. |
| fminnm | FMINNM <Hd|Sd|Dd>, <Hn|Sn|Dn>, <Hm|Sm|Dm> | FP Data Processing | Floating Point | Returns smaller value, handling NaNs according to IEEE 754-2008 'minNum'. |
| fminp | FMINP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Min of adjacent float elements. |
| fminv | FMINV <Vd>, <Pg>, <Zn>.<T> | SVE Reduction | SVE | Finds min float in vector. |
| fminv | FMINV <Sd>, <Vn>.<T> | NEON Reduction | NEON (v8.0) | Finds min float in a vector. |
| fmla | FMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Multiplies and adds to destination (Vd = Vd + Vn * Vm). |
| fmla | FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T> | SVE FP Ternary | SVE | Calculates (Zda + Zn * Zm) under predicate. |
| fmla | FMLA <Vd>.8H, <Vn>.8H, <Vm>.8H | NEON FP16 | FEAT_FP16 (NEON) | Fused multiply-add on half-precision vectors. |