ARM Instructions
1145 instructions - showing 100 per page, page 2 of 12 - click any row to view encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Extension | Summary |
|---|---|---|---|---|
| bit | BIT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Inserts bits from Vn into Vd where Vm (mask) is 1. |
| bkpt | BKPT #<imm> | Thumb System | T32 (Thumb) | Software Breakpoint (Thumb encoding). |
| bkpt | BKPT #<imm> | System | A32 (Base) | Causes a software breakpoint. |
| bl | BL <label> | Branch | Base | Function call. Branches to label and stores return address in LR (X30). |
| bl | BL<c> <label> | Branch | A32 (Base) | Calls a subroutine, storing return address in LR (R14). |
| bl.w | BL.W <label> | Thumb Branch | T32 (Thumb2) | Thumb-2 32-bit Branch with Link. |
| blr | BLR <Xn> | Branch (Reg) | Base | Indirect function call. Branches to address in Xn and stores return in LR. |
| blx | BLX<c> <Rm> | Branch | A32 (Base) | Calls subroutine and optionally switches to Thumb state. |
| br | BR <Xn> | Branch (Reg) | Base | Indirect branch to address in Xn. |
| brb | BRB <op> | System | FEAT_BRBE (Debug) | Injects an entry into the Branch Record Buffer (Debug). |
| brk | BRK #<imm> | Exception | Base | Generates a Breakpoint instruction exception. |
| brka | BRKA <Pd>.B, <Pg>/Z, <Pn>.B | SVE Predicate | SVE | Sets predicates up to and including the first active element. |
| brkb | BRKB <Pd>.B, <Pg>/Z, <Pn>.B | SVE Predicate | SVE | Sets predicates up to (but excluding) the first active element. |
| bsl | BSL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Selects bits from Vn or Vm based on Vd (mask). (Vd = (Vd & Vn) | (~Vd & Vm)). |
| bti | BTI <target> | System Hint | BTI (Security) | Marks a valid target for indirect branches (Guard against JOP/ROP). |
| bti | BTI {<target>} | System | BTI (Security) | Mark a valid target for an indirect branch (Control Flow Integrity). |
| bx | BX<c> <Rm> | Branch | A32 (Base) | Branches to address in register, optionally switching ISA. |
| bxj | BXJ<c> <Rm> | Branch | A32 (Legacy) | Legacy instruction to enter Jazelle state (Now behaves like BX). |
| cas | CAS <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic Compare and Swap (32-bit). |
| cas | CAS <Xs>, <Xt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic Compare and Swap (64-bit). |
| casa | CASA <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Acquire semantics. |
| casal | CASAL <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Acquire and Release semantics. |
| casl | CASL <Ws>, <Wt>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS with Release semantics. |
| casp | CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>] | Atomic | LSE (Atomics) | Atomic CAS of a pair of registers (128-bit or 64-bit pair). |
| cbnz | CBNZ <Wt>, <label> | Branch | Base | Branches if register is not zero. |
| cbnz | CBNZ <Xt>, <label> | Branch | Base | Branches if 64-bit register is not zero. |
| cbnz | CBNZ <Rn>, <label> | Thumb Branch | T32 (Thumb) | Branches to label if register is not zero (Thumb-only). |
| cbz | CBZ <Wt>, <label> | Branch | Base | Branches if register is zero. |
| cbz | CBZ <Xt>, <label> | Branch | Base | Branches if 64-bit register is zero. |
| cbz | CBZ <Rn>, <label> | Thumb Branch | T32 (Thumb) | Branches to label if register is zero (Thumb-only, does not affect flags). |
| ccmn | CCMN <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares register with negative immediate if condition is true. |
| ccmn | CCMN <Xn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares 64-bit register with negative immediate if condition is true. |
| ccmn | CCMN <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Base | Compares two registers (negated) if condition is true. |
| ccmp | CCMP <Wn>, #<imm>, #<nzcv>, <cond> | Cond Comp | Base | Compares register with immediate if condition is true. |
| ccmp | CCMP <Wn>, <Wm>, #<nzcv>, <cond> | Cond Comp | Base | Compares two registers if condition is true. |
| cdp | CDP<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | A32 (System) | Initiates a coprocessor data processing operation. |
| cdp2 | CDP2<c> <coproc>, <opc1>, <CRd>, <CRn>, <CRm>, <opc2> | Coprocessor | A32 (System) | Initiates a coprocessor operation (Extension encoding). |
| cfinv | CFINV | System | FEAT_FlagM | Inverts the C (Carry) flag. |
| chkfeat | CHK <#imm> | System | FEAT_CHK | Check feature status (FEAT_CHK). |
| cinc | CINC <Wd>, <Wn>, <cond> | Cond Select | Base | Increment register if condition is true, else copy. (Alias for CSINC) |
| cinv | CINV <Wd>, <Wn>, <cond> | Cond Select | Base | Invert register bits if condition is true, else copy. (Alias for CSINV) |
| clasta | CLASTA <Rdn>, <Pg>, <Rdn>, <Zm>.<T> | SVE Extract | SVE | Extracts element after the last active element. |
| clastb | CLASTB <Rdn>, <Pg>, <Rdn>, <Zm>.<T> | SVE Extract | SVE | Extracts the last active element. |
| clrex | CLREX | Thumb System | A32 (Atomic) | Clears exclusive monitor (Thumb). |
| clrex | CLREX {#<imm>} | System | Base (Atomic) | Clears the local monitor state (AArch64 variant). |
| clrex | CLREX<c> | System | A32 (Base) | Clears the local exclusive access monitor. |
| cls | CLS <Wd>, <Wn> | Data Processing | Base | Counts number of consecutive sign bits. |
| clz | CLZ <Wd>, <Wn> | Data Processing | Base | Counts number of consecutive zeros. |
| clz | CLZ <Rd>, <Rm> | Thumb Misc | A32 (Base) | Counts consecutive zeros. |
| clz | CLZ<c> <Rd>, <Rm> | Data Proc | A32 (Base) | Counts the number of consecutive zeros from MSB. |
| clz | CLZ <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Counts leading zeros for each element. |
| cmeq | CMEQ <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn == Vm) and sets bits to all 1s or 0s. |
| cmge | CMGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn >= Vm). |
| cmgt | CMGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Compares elements (Vn > Vm) and sets bits to all 1s or 0s. |
| cmn | CMN <Wn>, #<imm> | Data Processing | Base | Adds register and immediate, updates flags (discard result). (Alias for ADDS) |
| cmn | CMN<c> <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Adds two values and updates flags (discarding result). Same as ADDS with no destination. |
| cmn.w | CMN.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Compare Negative (Add and update flags). |
| cmp | CMP <Wn>, #<imm> | Data Processing | Base | Subtracts immediate from register, updates flags (discard result). (Alias for SUBS) |
| cmp | CMP<c> <Rn>, <Rm> {, <shift>} | Data Proc | A32 (Base) | Subtracts two values and updates flags (discarding result). |
| cmp.w | CMP.W <Rn>, <Operand2> | Thumb2 Data Proc | T32 (Thumb2) | Thumb-2 32-bit Compare (Subtract and update flags). |
| cmpeq | CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE Compare | SVE | Sets predicate bits where elements are equal. |
| cmpgt | CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T> | SVE Compare | SVE | Sets predicate bits where Zn > Zm. |
| cmtst | CMTST <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | SIMD Three Register | NEON (SIMD) | Tests if any bits match ((Vn & Vm) != 0). |
| cneg | CNEG <Wd>, <Wn>, <cond> | Cond Select | Base | Negate register if condition is true, else copy. (Alias for CSNEG) |
| cnt | CNT <Vd>.<T>, <Vn>.<T> | SIMD Two Register | NEON (SIMD) | Counts set bits (population count) per byte. |
| cntp | CNTP <Xn>, <Pg>, <Pn>.<T> | SVE Count | SVE | Counts the number of true elements in a predicate. |
| compact | COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> | SVE Permute | SVE | Packs active elements to the bottom of the vector. |
| cosp | COSP <Xt> | System | FEAT_CSV3 (Speculation) | Prevents speculation from determining that the instruction is executed. |
| cpp | CPPP <Xt> | System | FEAT_CPP | Prevents cache prefetch prediction past this instruction. |
| cps | CPS<effect> <iflags> {, #<mode>} | System | A32 (System) | Changes the processor mode or interrupt masks. |
| cps | CPS<effect> <iflags> {, #<mode>} | Thumb System | T32 (System) | Change mode/state (Thumb). |
| cpy | CPY <Zd>.<T>, <Pg>/M, <R><n> | SVE Move | SVE | Copies scalar value to active vector elements (Alias for DUP predicated). |
| cpy | CPY <Zd>.<T>, <Pg>/M, <Zn>.<T> | SVE2 Move | SVE2 | Copies data from source to destination using SVE vector length. |
| crc32b | CRC32B<c> <Rd>, <Rn>, <Rm> | Data Proc | CRC | CRC32 checksum update (Byte). |
| crc32b | CRC32B <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32 checksum with a byte. |
| crc32cb | CRC32CB <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32C (Castagnoli) checksum with a byte. |
| crc32w | CRC32W<c> <Rd>, <Rn>, <Rm> | Data Proc | CRC | CRC32 checksum update (Word). |
| crc32w | CRC32W <Wd>, <Wn>, <Wm> | Data Processing | CRC | Updates CRC32 checksum with a word. |
| crc32x | CRC32X <Wd>, <Wn>, <Xm> | Data Processing | CRC | Updates CRC32 checksum with a doubleword (64-bit). |
| csdb | CSDB | System Hint | A32 (v8.0) | Prevents speculative data consumption (v8.0). |
| csdb | CSDB | System Hint | Base | Prevents speculative data consumption. |
| csel | CSEL <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects between two registers based on condition. |
| cset | CSET <Wd>, <cond> | Cond Select | Base | Sets register to 1 if condition true, else 0. (Alias for CSINC) |
| csinc | CSINC <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else (Wm + 1). |
| csinv | CSINV <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else NOT Wm. |
| csneg | CSNEG <Wd>, <Wn>, <Wm>, <cond> | Cond Select | Base | Selects Wn if cond true, else -Wm. |
| dbg | DBG #<option> | System Hint | A32 (Base) | Provides a hint to the debug system. |
| dbg | DBG #<option> | Thumb System | T32 (Base) | Debug hint (Thumb). |
| dc | DC <op>, <Xt> | System Alias | System | Performs data cache maintenance (Clean, Invalidate, Flush). |
| dcps1 | DCPS1 | System | A32 (System) | Switches execution to EL1 (Debug). |
| dcps1 | DCPS1 {#<imm>} | Exception | System | Switch to Exception Level 1 (Debug). |
| dcps2 | DCPS2 | System | A32 (System) | Switches execution to EL2 (Debug). |
| dcps2 | DCPS2 {#<imm>} | Exception | System | Switch to Exception Level 2 (Debug). |
| dcps3 | DCPS3 | System | A32 (System) | Switches execution to EL3 (Debug). |
| dcps3 | DCPS3 {#<imm>} | Exception | System | Switch to Exception Level 3 (Debug). |
| decb | DECB <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active bytes. |
| decd | DECD <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active doublewords. |
| decw | DECW <Xdn>, <pattern> {, MUL #<imm>} | SVE Inc/Dec | SVE | Decrements a register by the number of active words. |
| dfb | DFB | System Hint | A32 (Legacy) | Deprecated alias for DSB. |
| dgh | DGH | System Hint | Base | Hints that multiple memory accesses should be merged. |