bfmlalt

BFMLALT <Zda>.S, <Zn>.H, <Zm>.H

BFloat16 Multiply-Add Long (Top)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
011001001
31:23
1
22
1
21
Zm
20:16
10
15:14
0
13
00
12:11
1
10
Zn
9:5
Zda
4:0
 
Format BF16
Opcode 0x64E08400
Extension BF16

Related

More in BF16

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x64E08400 BFMLALT <Zda>.S, <Zn>.H, <Zm>.H A64 011001001 | 1 | 1 | Zm | 10 | 0 | 00 | 1 | Zn | Zda
0x64E04400 BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>] A64 011001001 | 1 | 1 | i3h | Zm | 01 | 0 | 0 | i3l | 1 | Zn | Zda

Description

This BFloat16 floating-point multiply-add long instruction widens the odd-numbered BFloat16 elements in the first source vector and the corresponding elements in the second source vector to single-precision format and then destructively multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors. This instruction is unpredicated. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 32;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;

for e = 0 to elements-1
    bits(16) element1 = Elem[operand1, 2 * e + 1, 16];
    bits(16) element2 = Elem[operand2, 2 * e + 1, 16];
    bits(32) element3 = Elem[operand3, e, 32];
    Elem[result, e, 32] = BFMulAddH(element3, element1, element2, FPCR);

Z[da, VL] = result;