bfcvtnt

BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S

BFloat16 Convert Narrow (Top)

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01100100
31:24
1
23
0
22
0010
21:18
1
17
0
16
101
15:13
Pg
12:10
Zn
9:5
Zd
4:0
 
Format BF16
Opcode 0x648AA000
Extension BF16

Related

More in BF16

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x648AA000 BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S A64 01100100 | 1 | 0 | 0010 | 1 | 0 | 101 | Pg | Zn | Zd

Description

Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the odd-numbered 16-bit elements of the destination vector, leaving the even-numbered elements unchanged. Inactive elements in the destination vector register remain unmodified. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 32;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, 32) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, 32) then
        bits(32) element = Elem[operand, e, 32];
        Elem[result, 2*e+1, 16] = FPConvertBF(element, FPCR);

Z[d, VL] = result;