bfmmla

BFMMLA <Zda>.S, <Zn>.H, <Zm>.H

BFloat16 Matrix Multiply-Add.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01100100
31:24
0
23
1
22
1
21
Zm
20:16
111001
15:10
Zn
9:5
Zda
4:0
 
Format BF16
Opcode 0x6460E400
Extension BF16

Related

Other forms of bfmmla

  • bfmmla BFloat16 Matrix Multiply-Accumulate (NEON)

More in BF16

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x6E40EC00 BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H A64 0 | 1 | 1 | 01110 | 01 | 0 | Rm | 1 | 1101 | 1 | Rn | Rd
0x6460E400 BFMMLA <Zda>.S, <Zn>.H, <Zm>.H A64 01100100 | 0 | 1 | 1 | Zm | 111001 | Zn | Zda

Description

If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction: Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: This instruction is unpredicated and vector length agnostic. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented. This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer segments =  VL DIV 128;
bits(VL) operand1 = Z[n, VL];
bits(VL) operand2 = Z[m, VL];
bits(VL) operand3 = Z[da, VL];
bits(VL) result;
bits(128) op1, op2;
bits(128) res, addend;

for s = 0 to segments-1
    op1    = Elem[operand1, s, 128];
    op2    = Elem[operand2, s, 128];
    addend = Elem[operand3, s, 128];
    res    = BFMatMulAdd(addend, op1, op2,  FPCR);
    Elem[result, s, 128] = res;

Z[da, VL] = result;