bfcvt

BFCVT <Zd>.H, <Pg>/M, <Zn>.S

BFloat16 Convert from Float.

Pseudocode Operation

No pseudocode available.

Encoding

Binary Layout
01100101
31:24
1
23
0
22
0010
21:18
1
17
0
16
101
15:13
Pg
12:10
Zn
9:5
Zd
4:0
 
Format BF16
Opcode 0x658AA000
Extension BF16

Related

More in BF16

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1E634000 BFCVT <Hd>, <Sn> A64 0 | 0 | 0 | 11110 | 01 | 1 | 000110 | 10000 | Rn | Rd
0xC164E000 BFCVT <Zd>.B, { <Zn1>.H-<Zn2>.H } A64 110000010 | 1 | 100100111000 | Zn | 0 | Zd
0xC160E000 BFCVT <Zd>.H, { <Zn1>.S-<Zn2>.S } A64 110000010 | 1 | 100000111000 | Zn | 0 | Zd
0x658AA000 BFCVT <Zd>.H, <Pg>/M, <Zn>.S A64 01100101 | 1 | 0 | 0010 | 1 | 0 | 101 | Pg | Zn | Zd

Description

Convert to BFloat16 from single-precision in each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified. Since the result type is smaller than the input type, the results are zero-extended to fill each destination element. ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 32;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, 32) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, 32) then
        bits(32) element = Elem[operand, e, 32];
        Elem[result, 2*e, 16] = FPConvertBF(element, FPCR);
        Elem[result, 2*e+1, 16] = Zeros(16);

Z[d, VL] = result;