AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 13 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| s_wait_asynccnt | s_wait_asynccnt | SOPP | Wait until ASYNCCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_bvhcnt | s_wait_bvhcnt | SOPP | Wait until BVHCNT is less than or equal to SIMM16[2:0]. | ||
| s_wait_dscnt | s_wait_dscnt | SOPP | Wait until DSCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_event | s_wait_event | SOPP | gfx1100 | Wait for an event to occur or a condition to be satisfied before continuing. The SIMM16 argument specifies which event(s) to wait on. | |
| s_wait_expcnt | s_wait_expcnt | SOPP | Wait until EXPCNT is less than or equal to SIMM16[2:0]. | ||
| s_wait_idle | s_wait_idle | SOPP | Wait for all activity in the wave to be complete (all dependency and memory counters at zero). | ||
| s_wait_kmcnt | s_wait_kmcnt | SOPP | Wait until KMCNT is less than or equal to SIMM16[4:0]. | ||
| s_wait_loadcnt | s_wait_loadcnt | SOPP | Wait until LOADCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_loadcnt_dscnt | s_wait_loadcnt_dscnt | SOPP | Wait until LOADCNT is less than or equal to SIMM16[13:8] and DSCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_samplecnt | s_wait_samplecnt | SOPP | Wait until SAMPLECNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_storecnt | s_wait_storecnt | SOPP | Wait until STORECNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_storecnt_dscnt | s_wait_storecnt_dscnt | SOPP | Wait until STORECNT is less than or equal to SIMM16[13:8] and DSCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_tensorcnt | s_wait_tensorcnt | SOPP | Wait until TENSORCNT is less than or equal to SIMM16[5:0]. | ||
| s_wait_xcnt | s_wait_xcnt | SOPP | Wait until XCNT is less than or equal to SIMM16[5:0]. | ||
| s_waitcnt | s_waitcnt | SOPP | gfx1100 | Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels. | |
| s_waitcnt_depctr | s_waitcnt_depctr | SOPP | Wait for one or more ALU-centric counters to fall below specified values. Used in expert scheduling mode. | ||
| s_waitcnt_expcnt | s_waitcnt_expcnt | SOPK | gfx1100 | Wait for the EXPCNT counter to be at or below the specified level. The EXPCNT counter tracks the number of outstanding export events. | |
| s_waitcnt_lgkmcnt | s_waitcnt_lgkmcnt | SOPK | gfx1100 | Wait for the LGKMCNT counter to be at or below the specified level. | |
| s_waitcnt_vmcnt | s_waitcnt_vmcnt | SOPK | gfx1100 | Wait for the VMCNT counter to be at or below the specified level. | |
| s_waitcnt_vscnt | s_waitcnt_vscnt | SOPK | gfx1100 | Wait for the VSCNT counter to be at or below the specified level. | |
| s_wakeup | s_wakeup | SOPP | gfx1100 | Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction. | |
| s_wakeup_barrier | s_wakeup_barrier | SOP1 | AMDGPU SOP1 scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| s_wqm_b32 | s_wqm_b32 | SOP1 | gfx1100 | Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff… | |
| s_wqm_b64 | s_wqm_b64 | SOP1 | gfx1100 | Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff… | |
| s_xnor_b32 | s_xnor_b32 | SOP2 | gfx1100 | Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_xnor_b64 | s_xnor_b64 | SOP2 | gfx1100 | Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. | |
| s_xnor_saveexec_b32 | s_xnor_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_xnor_saveexec_b64 | s_xnor_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_xor_b32 | s_xor_b32 | SOP2 | gfx1100 | Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_xor_b64 | s_xor_b64 | SOP2 | gfx1100 | Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. | |
| s_xor_saveexec_b32 | s_xor_saveexec_b32 | SOP1 | gfx1100 | Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| s_xor_saveexec_b64 | s_xor_saveexec_b64 | SOP1 | gfx1100 | Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is… | |
| scratch_load_block | scratch_load_block | SCRATCH | Load a block of data from the scratch aperture. | ||
| scratch_load_dword | scratch_load_dword | SCRATCH | Load 32 bits of data from the scratch aperture into a vector register. | ||
| scratch_load_dwordx2 | scratch_load_dwordx2 | SCRATCH | Load 64 bits of data from the scratch aperture into a vector register. | ||
| scratch_load_dwordx3 | scratch_load_dwordx3 | SCRATCH | Load 96 bits of data from the scratch aperture into a vector register. | ||
| scratch_load_dwordx4 | scratch_load_dwordx4 | SCRATCH | Load 128 bits of data from the scratch aperture into a vector register. | ||
| scratch_load_lds_dword | scratch_load_lds_dword | SCRATCH | Load 32 bits of untyped data from the scratch aperture and store the result into a data share. | ||
| scratch_load_lds_sbyte | scratch_load_lds_sbyte | SCRATCH | Load 8 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_sshort | scratch_load_lds_sshort | SCRATCH | Load 16 bits of untyped data from the scratch aperture, sign extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_ubyte | scratch_load_lds_ubyte | SCRATCH | Load 8 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share. | ||
| scratch_load_lds_ushort | scratch_load_lds_ushort | SCRATCH | Load 16 bits of untyped data from the scratch aperture, zero extend to 32 bits and store the result into a data share. | ||
| scratch_load_sbyte | scratch_load_sbyte | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. | ||
| scratch_load_sbyte_d16 | scratch_load_sbyte_d16 | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_sbyte_d16_hi | scratch_load_sbyte_d16_hi | SCRATCH | Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_short_d16 | scratch_load_short_d16 | SCRATCH | Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_short_d16_hi | scratch_load_short_d16_hi | SCRATCH | Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_sshort | scratch_load_sshort | SCRATCH | Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. | ||
| scratch_load_ubyte | scratch_load_ubyte | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. | ||
| scratch_load_ubyte_d16 | scratch_load_ubyte_d16 | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. | ||
| scratch_load_ubyte_d16_hi | scratch_load_ubyte_d16_hi | SCRATCH | Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. | ||
| scratch_load_ushort | scratch_load_ushort | SCRATCH | Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. | ||
| scratch_store_block | scratch_store_block | SCRATCH | Store a block of data to the scratch aperture. | ||
| scratch_store_byte | scratch_store_byte | SCRATCH | Store 8 bits of data from a vector register into the scratch aperture. | ||
| scratch_store_byte_d16_hi | scratch_store_byte_d16_hi | SCRATCH | Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. | ||
| scratch_store_dword | scratch_store_dword | SCRATCH | Store 32 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx2 | scratch_store_dwordx2 | SCRATCH | Store 64 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx3 | scratch_store_dwordx3 | SCRATCH | Store 96 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_dwordx4 | scratch_store_dwordx4 | SCRATCH | Store 128 bits of data from vector input registers into the scratch aperture. | ||
| scratch_store_short | scratch_store_short | SCRATCH | Store 16 bits of data from a vector register into the scratch aperture. | ||
| scratch_store_short_d16_hi | scratch_store_short_d16_hi | SCRATCH | Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. | ||
| tbuffer_load_d16_format_x | tbuffer_load_d16_format_x | MTBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xy | tbuffer_load_d16_format_xy | MTBUF | gfx1100 | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xyz | tbuffer_load_d16_format_xyz | MTBUF | gfx1100 | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_d16_format_xyzw | tbuffer_load_d16_format_xyzw | MTBUF | gfx1100 | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | |
| tbuffer_load_format_d16_x | tbuffer_load_format_d16_x | MTBUF | Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xy | tbuffer_load_format_d16_xy | MTBUF | Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xyz | tbuffer_load_format_d16_xyz | MTBUF | Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_d16_xyzw | tbuffer_load_format_d16_xyzw | MTBUF | Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result… | ||
| tbuffer_load_format_x | tbuffer_load_format_x | MTBUF | gfx1100 | Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xy | tbuffer_load_format_xy | MTBUF | gfx1100 | Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xyz | tbuffer_load_format_xyz | MTBUF | gfx1100 | Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_load_format_xyzw | tbuffer_load_format_xyzw | MTBUF | gfx1100 | Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a… | |
| tbuffer_store_d16_format_x | tbuffer_store_d16_format_x | MTBUF | gfx1100 | Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xy | tbuffer_store_d16_format_xy | MTBUF | gfx1100 | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xyz | tbuffer_store_d16_format_xyz | MTBUF | gfx1100 | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_d16_format_xyzw | tbuffer_store_d16_format_xyzw | MTBUF | gfx1100 | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_d16_x | tbuffer_store_format_d16_x | MTBUF | Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xy | tbuffer_store_format_d16_xy | MTBUF | Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xyz | tbuffer_store_format_d16_xyz | MTBUF | Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_d16_xyzw | tbuffer_store_format_d16_xyzw | MTBUF | Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | ||
| tbuffer_store_format_x | tbuffer_store_format_x | MTBUF | gfx1100 | Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xy | tbuffer_store_format_xy | MTBUF | gfx1100 | Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xyz | tbuffer_store_format_xyz | MTBUF | gfx1100 | Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. | |
| tbuffer_store_format_xyzw | tbuffer_store_format_xyzw | MTBUF | gfx1100 | Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. | |
| tensor_load_to_lds | tensor_load_to_lds | MIMG | DMA instruction to load tensor data from Global to LDS. | ||
| tensor_save | tensor_save | FLAT | AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| tensor_stop | tensor_stop | FLAT | AMDGPU FLAT vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| tensor_store_from_lds | tensor_store_from_lds | MIMG | DMA instruction to store tensor data to Global from LDS. | ||
| v_accvgpr_mov_b32 | v_accvgpr_mov_b32 | VOP1 | Move data from one accumulator register to another accumulator register. | ||
| v_accvgpr_read_b32 | v_accvgpr_read_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_accvgpr_write_b32 | v_accvgpr_write_b32 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add3_u32 | v_add3_u32 | VOP3 | gfx1100 | Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_co_ci_u32 | v_add_co_ci_u32 | VOP2 | Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a… | ||
| v_add_co_u32 | v_add_co_u32 | VOP2 | gfx1100 | Add two unsigned 32-bit integer inputs, store the result into a vector register and store the carry-out mask into a scalar register. | |
| v_add_f16 | v_add_f16 | VOP2 | gfx1100 | Add two floating point inputs and store the result into a vector register. | |
| v_add_f32 | v_add_f32 VDST, S0, S1 | VOP2 | gfx942, gfx1100 | Vector ALU | Per-lane single-precision floating-point add. |
| v_add_f64 | v_add_f64 | VOP2 | gfx1100 | Add two floating point inputs and store the result into a vector register. | |
| v_add_f64_pseudo | v_add_f64_pseudo | VOP2 | AMDGPU VOP2 vector instruction operating on f64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_i16 | v_add_i16 | VOP3 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗