AMDGPU / GFX Instructions GPU Native ISA AMD
1960 instructions - showing 100 per page, page 13 of 20 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_cmpx_gt_f16 | v_cmpx_gt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_f32 | v_cmpx_gt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_f64 | v_cmpx_gt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_i16 | v_cmpx_gt_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_i32 | v_cmpx_gt_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_i64 | v_cmpx_gt_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_u16 | v_cmpx_gt_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_u32 | v_cmpx_gt_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_gt_u64 | v_cmpx_gt_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. | |
| v_cmpx_le_f16 | v_cmpx_le_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_f32 | v_cmpx_le_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_f64 | v_cmpx_le_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_i16 | v_cmpx_le_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_i32 | v_cmpx_le_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_i64 | v_cmpx_le_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_u16 | v_cmpx_le_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_u32 | v_cmpx_le_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_le_u64 | v_cmpx_le_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. | |
| v_cmpx_lg_f16 | v_cmpx_lg_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmpx_lg_f32 | v_cmpx_lg_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmpx_lg_f64 | v_cmpx_lg_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmpx_lt_f16 | v_cmpx_lt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_f32 | v_cmpx_lt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_f64 | v_cmpx_lt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_i16 | v_cmpx_lt_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_i32 | v_cmpx_lt_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_i64 | v_cmpx_lt_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_u16 | v_cmpx_lt_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_u32 | v_cmpx_lt_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_lt_u64 | v_cmpx_lt_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. | |
| v_cmpx_ne_i16 | v_cmpx_ne_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_ne_i32 | v_cmpx_ne_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_ne_i64 | v_cmpx_ne_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_ne_u16 | v_cmpx_ne_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_ne_u32 | v_cmpx_ne_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_ne_u64 | v_cmpx_ne_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_neq_f16 | v_cmpx_neq_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_neq_f32 | v_cmpx_neq_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_neq_f64 | v_cmpx_neq_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not equal to the second input. | |
| v_cmpx_nge_f16 | v_cmpx_nge_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmpx_nge_f32 | v_cmpx_nge_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmpx_nge_f64 | v_cmpx_nge_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than or equal to the second input. | |
| v_cmpx_ngt_f16 | v_cmpx_ngt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. | |
| v_cmpx_ngt_f32 | v_cmpx_ngt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. | |
| v_cmpx_ngt_f64 | v_cmpx_ngt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not greater than the second input. | |
| v_cmpx_nle_f16 | v_cmpx_nle_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmpx_nle_f32 | v_cmpx_nle_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmpx_nle_f64 | v_cmpx_nle_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or equal to the second input. | |
| v_cmpx_nlg_f16 | v_cmpx_nlg_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmpx_nlg_f32 | v_cmpx_nlg_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmpx_nlg_f64 | v_cmpx_nlg_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than or greater than the second input. | |
| v_cmpx_nlt_f16 | v_cmpx_nlt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. | |
| v_cmpx_nlt_f32 | v_cmpx_nlt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. | |
| v_cmpx_nlt_f64 | v_cmpx_nlt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not less than the second input. | |
| v_cmpx_o_f16 | v_cmpx_o_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. | |
| v_cmpx_o_f32 | v_cmpx_o_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. | |
| v_cmpx_o_f64 | v_cmpx_o_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is orderable to the second input. | |
| v_cmpx_t_f16 | v_cmpx_t_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask. | |
| v_cmpx_t_f32 | v_cmpx_t_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask. | |
| v_cmpx_t_f64 | v_cmpx_t_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask. | |
| v_cmpx_t_i16 | v_cmpx_t_i16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_t_i32 | v_cmpx_t_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_i64 | v_cmpx_t_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_u16 | v_cmpx_t_u16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_t_u32 | v_cmpx_t_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_t_u64 | v_cmpx_t_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | |
| v_cmpx_tru_f16 | v_cmpx_tru_f16 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_tru_f32 | v_cmpx_tru_f32 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_tru_f64 | v_cmpx_tru_f64 | VOPC | Set the per-lane condition code to 1. Store the result into the EXEC mask and to VCC or a scalar register. | ||
| v_cmpx_u_f16 | v_cmpx_u_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cmpx_u_f32 | v_cmpx_u_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cmpx_u_f64 | v_cmpx_u_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is not orderable to the second input. | |
| v_cndmask_b16 | v_cndmask_b16 | VOP3 | gfx1100 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. | |
| v_cndmask_b16_fake16 | v_cndmask_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cndmask_b16_t16 | v_cndmask_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cndmask_b32 | v_cndmask_b32 | VOP2 | gfx1100 | Copy data from one of two inputs based on the per-lane condition code and store the result into a vector register. | |
| v_cos_bf16 | v_cos_bf16 | VOP1 | AMDGPU VOP1 vector instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cos_f16 | v_cos_f16 | VOP1 | gfx1100 | Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. | |
| v_cos_f32 | v_cos_f32 | VOP1 | gfx1100 | Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. | |
| v_cubeid_f32 | v_cubeid_f32 | VOP3 | gfx1100 | Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubema_f32 | v_cubema_f32 | VOP3 | gfx1100 | Compute the cubemap major axis of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubesc_f32 | v_cubesc_f32 | VOP3 | gfx1100 | Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. | |
| v_cubetc_f32 | v_cubetc_f32 | VOP3 | gfx1100 | Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. | |
| v_cvt_f16_bf8 | v_cvt_f16_bf8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_f32 | v_cvt_f16_f32 | VOP1 | gfx1100 | Convert from a single-precision float input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f16_f32_fake16 | v_cvt_f16_f32_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_f32_t16 | v_cvt_f16_f32_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_fp8 | v_cvt_f16_fp8 | VOP1 | AMDGPU VOP1 vector instruction operating on f16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f16_i16 | v_cvt_f16_i16 | VOP1 | gfx1100 | Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f16_u16 | v_cvt_f16_u16 | VOP1 | gfx1100 | Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register. | |
| v_cvt_f32_bf16 | v_cvt_f32_bf16 | VOP1 | Convert from a BF16 float input to a single-precision float value and store the result into a vector register. | ||
| v_cvt_f32_bf8 | v_cvt_f32_bf8 | VOP1 | gfx1100 | Convert from a BF8 float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_bf8_op_sel | v_cvt_f32_bf8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f16 | v_cvt_f32_f16 | VOP1 | gfx1100 | Convert from a half-precision float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_f16_fake16 | v_cvt_f32_f16_fake16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f16_t16 | v_cvt_f32_f16_t16 | VOP1 | AMDGPU VOP1 vector instruction operating on f16/f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_f64 | v_cvt_f32_f64 | VOP1 | gfx1100 | Convert from a double-precision float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_fp8 | v_cvt_f32_fp8 | VOP1 | gfx1100 | Convert from an FP8 float input to a single-precision float value and store the result into a vector register. | |
| v_cvt_f32_fp8_gfx1250 | v_cvt_f32_fp8_gfx1250 | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_cvt_f32_fp8_op_sel | v_cvt_f32_fp8_op_sel | VOP1 | AMDGPU VOP1 vector instruction operating on f32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗