s_waitcnt_depctr GPU Native ISA AMD Scalar

Branch & Control

s_waitcnt_depctr

Wait for one or more ALU-centric counters to fall below specified values. Used in expert scheduling mode.

Also written as s_wait_alu. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
101111111
31:23
0001000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 8 in OP rebuilds 0xBF880000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 35), AMD RDNA 1 (opcode 35). The same in AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 8
Identifier 0xBF880000

Operands

  • SIMM16
    Read. A waitcnt operand for ALU and miscellaneous dependency counters. Data format: 16 bits of arbitrary data. (OPR_WAITCNT_DEPCTR, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD RDNA 3.5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_waitcnt_depctr 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_sop.s). Not from an AMD document, and not authored here.

Sources