s_sethalt GPU Native ISA AMD Scalar
S SETHALT Branch & Control
s_sethalt
Set or clear the HALT status bit.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Semantics
Set HALT bit to value of SIMM16[0]; 1 = halt, 0 = clear HALT bit. The halt flag is ignored while PRIV == 1 (inside
trap handlers) but the shader halts after the handler returns if HALT is still set at that time.
Example
s_sethalt 0x0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 141. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project