s_sethalt GPU Native ISA AMD Scalar

Branch & Control

s_sethalt

Set or clear the HALT status bit.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0000010
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 2 in OP rebuilds 0xBF820000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 13), AMD CDNA 3 (opcode 13), AMD CDNA 2 (opcode 13), AMD CDNA 1 (opcode 13), AMD RDNA 2 (opcode 13), AMD RDNA 1 (opcode 13). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 2
Identifier 0xBF820000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

Set HALT bit to value of SIMM16[0]; 1 = halt, 0 = clear HALT bit. The halt flag is ignored while PRIV == 1 (inside trap handlers) but the shader halts after the handler returns if HALT is still set at that time.

Example

s_sethalt 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources