s_endpgm_saved GPU Native ISA AMD Scalar

Branch & Control

s_endpgm_saved

End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0110001
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 49 in OP rebuilds 0xBFB10000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 27), AMD CDNA 3 (opcode 27), AMD CDNA 2 (opcode 27), AMD CDNA 1 (opcode 27), AMD RDNA 2 (opcode 27), AMD RDNA 1 (opcode 27). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 49
Identifier 0xBFB10000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM for additional variants.

Sources