s_cbranch_cdbguser GPU Native ISA AMD Scalar

Branch & Control

s_cbranch_cdbguser

If the user debug flag is set then jump to a constant offset relative to the current PC.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0011000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 24 in OP rebuilds 0xBF980000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 40), AMD RDNA 3 (opcode 40). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 2, AMD RDNA 1.

Format SOPP
Width 32 bits
Opcode 24
Identifier 0xBF980000

Operands

  • SIMM16
    Read. A relative jump offset. Data format: N/A (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_cbranch_cdbguser 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_sop.s). Not from an AMD document, and not authored here.

Sources