s_cbranch_scc1 GPU Native ISA AMD Scalar

Branch & Control

s_cbranch_scc1 offset

Conditional relative branch, taken when the SCC (scalar condition code) flag is set.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0100010
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 34 in OP rebuilds 0xBFA20000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 5), AMD CDNA 3 (opcode 5), AMD CDNA 2 (opcode 5), AMD CDNA 1 (opcode 5), AMD RDNA 2 (opcode 5), AMD RDNA 1 (opcode 5). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 34
Identifier 0xBFA20000
Execution Unit Scalar ALU

Operands

  • offset
    Signed word-granularity branch offset

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Branch ↗
equivalent with restrictions
bra (PTX)

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

If SCC is 1 then jump to a constant offset relative to the current PC.

Semantics

if (SCC == 1) PC = PC + 4 + signed_offset * 4.

Example

s_cbranch_scc1  label   // jump to label if SCC == 1

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources