s_inst_prefetch GPU Native ISA AMD Scalar

Branch & Control

s_inst_prefetch

Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch.

Also written as s_set_inst_prefetch_distance. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 2)
101111111
31:23
0100000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD RDNA 2). Opcode 32 in OP rebuilds 0xBFA00000, an identifier AMD lists for this encoding. The same in AMD RDNA 1.

Format SOPP
Width 32 bits
Opcode 32
Identifier 0xBFA00000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: N/A (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_inst_prefetch 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx10_asm_sop.s). Not from an AMD document, and not authored here.

Sources