s_sendmsghalt GPU Native ISA AMD Scalar

Branch & Control

s_sendmsghalt

Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0110111
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 55 in OP rebuilds 0xBFB70000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 17), AMD CDNA 3 (opcode 17), AMD CDNA 2 (opcode 17), AMD CDNA 1 (opcode 17), AMD RDNA 2 (opcode 17), AMD RDNA 1 (opcode 17). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 55
Identifier 0xBFB70000

Operands

  • SIMM16
    Read. Send a message back to SPI. Data format: 16 bits of arbitrary data. (OPR_SENDMSG, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_sendmsghalt 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources