s_sendmsghalt GPU Native ISA AMD Scalar
S SENDMSGHALT Branch & Control
s_sendmsghalt
Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Example
s_sendmsghalt 0x0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 142. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project