s_sleep GPU Native ISA AMD Scalar

Branch & Control

s_sleep

Cause a wave to sleep for up to ~8000 clocks.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0000011
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 3 in OP rebuilds 0xBF830000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 14), AMD CDNA 3 (opcode 14), AMD CDNA 2 (opcode 14), AMD CDNA 1 (opcode 14), AMD RDNA 2 (opcode 14), AMD RDNA 1 (opcode 14). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 3
Identifier 0xBF830000

Operands

  • SIMM16
    Read. SLEEP operand specifying duration and sleep-forever mode. Data format: 16 bits of arbitrary data. (OPR_SLEEP, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Examples: s_sleep 0 // Wait for 0 clocks. s_sleep 1 // Wait for 1-64 clocks. s_sleep 2 // Wait for 65-128 clocks.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Cause a wave to sleep for up to ~8000 clocks. The wave sleeps for (64*(SIMM16[6:0]-1) .. 64*SIMM16[6:0]) clocks. The exact amount of delay is approximate. Compare with S_NOP. When SIMM16[6:0] is zero then no sleep occurs.

Example

s_sleep 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources