s_wait_tensorcnt GPU Native ISA AMD Scalar

Branch & Control

s_wait_tensorcnt

Wait until TENSORCNT is less than or equal to SIMM16[5:0].

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
1001011
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 75 in OP rebuilds 0xBFCB0000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOPP
Width 32 bits
Opcode 75
Identifier 0xBFCB0000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_wait_tensorcnt 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopp.s). Not from an AMD document, and not authored here.

Sources