s_set_gpr_idx_mode GPU Native ISA AMD Scalar

Branch & Control

s_set_gpr_idx_mode

Modify the mode used for vector GPR indexing.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0011101
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 29 in OP rebuilds 0xBF9D0000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPP
Width 32 bits
Opcode 29
Identifier 0xBF9D0000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: N/A (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

The raw contents of the source field are read and used to set the enable bits. SIMM16[0] = VSRC0_REL, SIMM16[1] = VSRC1_REL, SIMM16[2] = VSRC2_REL and SIMM16[3] = VDST_REL. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions. M0[15 : 12] = SIMM16.u16[3 : 0].b4

Example

s_set_gpr_idx_mode 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_sopp.s). Not from an AMD document, and not authored here.

Sources