s_set_gpr_idx_mode GPU Native ISA AMD Scalar

S SET GPR IDX MODE Branch & Control

s_set_gpr_idx_mode

Modify the mode used for vector GPR indexing.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOPP) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOPP
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

The raw contents of the source field are read and used to set the enable bits. SIMM16[0] = VSRC0_REL, SIMM16[1] = VSRC1_REL, SIMM16[2] = VSRC2_REL and SIMM16[3] = VDST_REL. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions. M0[15 : 12] = SIMM16.u16[3 : 0].b4

Sources