s_cbranch_scc0 GPU Native ISA AMD Scalar

Branch & Control

s_cbranch_scc0

If SCC is 0 then jump to a constant offset relative to the current PC.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0100001
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 33 in OP rebuilds 0xBFA10000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 4), AMD CDNA 3 (opcode 4), AMD CDNA 2 (opcode 4), AMD CDNA 1 (opcode 4), AMD RDNA 2 (opcode 4), AMD RDNA 1 (opcode 4). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 33
Identifier 0xBFA10000

Operands

  • SIMM16
    Read. A relative jump offset. Data format: Signed 16-bit integral data. (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_cbranch_scc0 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopp.s). Not from an AMD document, and not authored here.

Sources