s_trap GPU Native ISA AMD Scalar

Branch & Control

s_trap

Enter the trap handler.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0010000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 16 in OP rebuilds 0xBF900000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 18), AMD CDNA 3 (opcode 18), AMD CDNA 2 (opcode 18), AMD CDNA 1 (opcode 18), AMD RDNA 2 (opcode 18), AMD RDNA 1 (opcode 18). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 16
Identifier 0xBF900000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Trap ↗
equivalent with restrictions
trap (PTX)

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

This instruction may be generated internally as well in response to a host trap (HT = 1) or an exception. TrapID 0 is reserved for hardware use and should not be used in a shader-generated trap. TrapID = SIMM16.u16[7 : 0]; "Wait for all instructions to complete"; // PC passed into trap handler points to S_TRAP itself, // *not* to the next instruction. { TTMP[1], TTMP[0] } = { 3'0, PCRewind[3 : 0], HT[0], TrapID[7 : 0], PC[47 : 0] }; PC = TBA.i64; // trap base address WAVE_STATUS.PRIV = 1'1U

Example

s_trap 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources