s_trap GPU Native ISA AMD Scalar

S TRAP Branch & Control

s_trap

Enter the trap handler.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOPP) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOPP
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Trap ↗
equivalent with restrictions
trap (PTX)

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

This instruction may be generated internally as well in response to a host trap (HT = 1) or an exception. TrapID 0 is reserved for hardware use and should not be used in a shader-generated trap. TrapID = SIMM16.u16[7 : 0]; "Wait for all instructions to complete"; // PC passed into trap handler points to S_TRAP itself, // *not* to the next instruction. { TTMP[1], TTMP[0] } = { 3'0, PCRewind[3 : 0], HT[0], TrapID[7 : 0], PC[47 : 0] }; PC = TBA.i64; // trap base address WAVE_STATUS.PRIV = 1'1U

Example

s_trap 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources