s_waitcnt GPU Native ISA AMD Scalar

Branch & Control

s_waitcnt

Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0001100
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 12 in OP rebuilds 0xBF8C0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 9), AMD RDNA 3 (opcode 9). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 2, AMD RDNA 1.

Format SOPP
Width 32 bits
Opcode 12
Identifier 0xBF8C0000

Operands

  • SIMM16
    Read. A waitcnt operand specifying expcnt, lgkmcnt and vmcnt. Data format: N/A (OPR_WAITCNT, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Semantics

SIMM16[3:0] = vmcount (vector memory operations) lower bits [3:0], SIMM16[6:4] = export/mem-write-data count, SIMM16[11:8] = LGKMcnt (scalar-mem/GDS/LDS count), SIMM16[15:14] = vmcount (vector memory operations) upper bits [5:4].

Example

s_waitcnt 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources