s_waitcnt GPU Native ISA AMD Scalar
S WAITCNT Branch & Control
s_waitcnt
Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Semantics
SIMM16[3:0] = vmcount (vector memory operations) lower bits [3:0],
SIMM16[6:4] = export/mem-write-data count,
SIMM16[11:8] = LGKMcnt (scalar-mem/GDS/LDS count),
SIMM16[15:14] = vmcount (vector memory operations) upper bits [5:4].
Example
s_waitcnt 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 141. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project