s_wait_bvhcnt GPU Native ISA AMD Scalar

Branch & Control

s_wait_bvhcnt

Wait until BVHCNT is less than or equal to SIMM16[2:0].

Encoding

Binary Layout (AMD RDNA 4)
101111111
31:23
1000011
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 67 in OP rebuilds 0xBFC30000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOPP
Width 32 bits
Opcode 67
Identifier 0xBFC30000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD RDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Sources