s_wait_event GPU Native ISA AMD Scalar

Branch & Control

s_wait_event

Wait for an event to occur or a condition to be satisfied before continuing. The SIMM16 argument specifies which event(s) to wait on.

Encoding

Binary Layout (AMD RDNA 4)
101111111
31:23
0001011
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 11 in OP rebuilds 0xBF8B0000, an identifier AMD lists for this encoding. The same in the other 2 generations that define it.

Format SOPP
Width 32 bits
Opcode 11
Identifier 0xBF8B0000

Operands

  • SIMM16
    Read. Specify one or more events to wait for. Data format: 16 bits of arbitrary data. (OPR_WAIT_EVENT, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD RDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_wait_event 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources