s_endpgm_ordered_ps_done GPU Native ISA AMD Scalar

Branch & Control

s_endpgm_ordered_ps_done

End of program; signal that a wave has exited its POPS critical section and terminate wavefront.

Encoding

Binary Layout (AMD CDNA 4)

101111111

31:23

0011110

22:16

SIMM16

15:0

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 30 in OP rebuilds 0xBF9E0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 50), AMD RDNA 3 (opcode 50). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 2, AMD RDNA 1.

Format SOPP

Width 32 bits

Opcode 30

Identifier 0xBF9E0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Reference

AMDGPU / GFX ISA

Sources

AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.