s_barrier_leave GPU Native ISA AMD Scalar

Branch & Control

s_barrier_leave

AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0010101
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 21 in OP rebuilds 0xBF950000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOPP
Width 32 bits
Opcode 21
Identifier 0xBF950000

Operands

  • 1: immediate
    Literal value encoded in the instruction. Written 0 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_barrier_leave 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopp.s). Not from an AMD document, and not authored here.

Sources