s_set_gpr_idx_off GPU Native ISA AMD Scalar
S SET GPR IDX OFF Branch & Control
s_set_gpr_idx_off
Clear GPR indexing mode.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Description
Clear GPR indexing mode. Vector operations after this do not perform relative GPR addressing regardless of the contents of M0. This instruction does not modify M0. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.
Semantics
WAVE_MODE.GPR_IDX_EN = 1'0U
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 145.