s_set_gpr_idx_off GPU Native ISA AMD Scalar

Branch & Control

s_set_gpr_idx_off

Clear GPR indexing mode.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0011100
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 28 in OP rebuilds 0xBF9C0000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPP
Width 32 bits
Opcode 28
Identifier 0xBF9C0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Clear GPR indexing mode. Vector operations after this do not perform relative GPR addressing regardless of the contents of M0. This instruction does not modify M0. S_SET_GPR_IDX_ON, S_SET_GPR_IDX_OFF, S_SET_GPR_IDX_MODE and S_SET_GPR_IDX_IDX are related instructions.

Semantics

WAVE_MODE.GPR_IDX_EN = 1'0U

Sources