s_wait_idle GPU Native ISA AMD Scalar

Branch & Control

s_wait_idle

Wait for all activity in the wave to be complete (all dependency and memory counters at zero).

Encoding

Binary Layout (AMD CDNA 5)

101111111

31:23

0001010

22:16

SIMM16

15:0

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 10 in OP rebuilds 0xBF8A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 1 (opcode 34). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP

Width 32 bits

Opcode 10

Identifier 0xBF8A0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Reference

AMDGPU / GFX ISA

Sources

AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.