s_wait_loadcnt_dscnt GPU Native ISA AMD Scalar

Branch & Control

s_wait_loadcnt_dscnt

Wait until LOADCNT is less than or equal to SIMM16[13:8] and DSCNT is less than or equal to SIMM16[5:0].

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
1001000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 72 in OP rebuilds 0xBFC80000, an identifier AMD lists for this encoding. The same in AMD RDNA 4.

Format SOPP
Width 32 bits
Opcode 72
Identifier 0xBFC80000

Operands

  • SIMM16
    Read. A waitcnt operand for combined memory (LOAD or STORE) and DS counter. Data format: 16 bits of arbitrary data. (OPR_WAIT_MEM_DS, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_wait_loadcnt_dscnt 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopp.s). Not from an AMD document, and not authored here.

Sources