s_set_valu_coexec_mode GPU Native ISA AMD Scalar

Branch & Control

s_set_valu_coexec_mode

Set the vector ALU co-execution mode to the value encoded in SIMM16[1:0] for the next VALU instruction.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0011111
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 31 in OP rebuilds 0xBF9F0000, an identifier AMD lists for this encoding. The same in AMD CDNA 3.

Format SOPP
Width 32 bits
Opcode 31
Identifier 0xBF9F0000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: N/A (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Set the vector ALU co-execution mode to the value encoded in SIMM16[1:0] for the next VALU instruction. The co-execution mode is cleared to zero after the next VALU instruction is issued.

Sources