s_code_end GPU Native ISA AMD Scalar

Branch & Control

s_code_end

Generate an illegal instruction interrupt. This instruction is used to mark the end of a shader buffer for debug tools.

Encoding

Binary Layout (AMD CDNA 5)

101111111

31:23

0011111

22:16

SIMM16

15:0

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 31 in OP rebuilds 0xBF9F0000, an identifier AMD lists for this encoding. The same in the other 5 generations that define it.

Format SOPP

Width 32 bits

Opcode 31

Identifier 0xBF9F0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Reference

AMDGPU / GFX ISA

Sources

AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.