s_endpgm GPU Native ISA AMD Scalar

Branch & Control

s_endpgm

End of program; terminate wavefront.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0110000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 48 in OP rebuilds 0xBFB00000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 1), AMD CDNA 3 (opcode 1), AMD CDNA 2 (opcode 1), AMD CDNA 1 (opcode 1), AMD RDNA 2 (opcode 1), AMD RDNA 1 (opcode 1). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 48
Identifier 0xBFB00000

Operands

  • 1: immediate
    Literal value encoded in the instruction. Written 1 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Kernel/Thread Exit ↗
equivalent with restrictions
exit (PTX)

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

End of program; terminate wavefront. The hardware implicitly executes S_WAITCNT 0 before executing this instruction. See S_ENDPGM_SAVED for the context-switch version of this instruction.

Example

s_endpgm 1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources