s_setkill GPU Native ISA AMD Scalar

Branch & Control

s_setkill

Kill this wave if the least significant bit of the immediate constant is 1. Used primarily for debugging kill wave host command behavior.

Encoding

Binary Layout (AMD CDNA 4)
101111111
31:23
0001011
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 11 in OP rebuilds 0xBF8B0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 4 (opcode 1), AMD RDNA 3.5 (opcode 1), AMD RDNA 3 (opcode 1). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1, AMD RDNA 2, AMD RDNA 1.

Format SOPP
Width 32 bits
Opcode 11
Identifier 0xBF8B0000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: N/A (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_setkill 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources