s_icache_inv GPU Native ISA AMD Scalar

Branch & Control

s_icache_inv

Invalidate entire first level instruction cache.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0111100
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 60 in OP rebuilds 0xBFBC0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 19), AMD CDNA 3 (opcode 19), AMD CDNA 2 (opcode 19), AMD CDNA 1 (opcode 19), AMD RDNA 2 (opcode 19), AMD RDNA 1 (opcode 19). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 60
Identifier 0xBFBC0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Invalidate entire first level instruction cache. There must be 16 separate S_NOP instructions or a jump/branch instruction after this instruction to ensure the internal instruction buffers are also invalidated.

Sources