s_icache_inv GPU Native ISA AMD Scalar
S ICACHE INV Branch & Control
s_icache_inv
Invalidate entire first level instruction cache.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Description
Invalidate entire first level instruction cache. There must be 16 separate S_NOP instructions or a jump/branch instruction after this instruction to ensure the internal instruction buffers are also invalidated.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 143.