s_ttracedata GPU Native ISA AMD Scalar

Branch & Control

s_ttracedata

Send M0 as user data to the thread trace stream.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0111010
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 58 in OP rebuilds 0xBFBA0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 22), AMD CDNA 3 (opcode 22), AMD CDNA 2 (opcode 22), AMD CDNA 1 (opcode 22), AMD RDNA 2 (opcode 22), AMD RDNA 1 (opcode 22). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 58
Identifier 0xBFBA0000

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Sources