s_wakeup GPU Native ISA AMD Scalar

Branch & Control

s_wakeup

Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0110100
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 52 in OP rebuilds 0xBFB40000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 3), AMD CDNA 3 (opcode 3), AMD CDNA 2 (opcode 3), AMD CDNA 1 (opcode 3), AMD RDNA 2 (opcode 3), AMD RDNA 1 (opcode 3). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 52
Identifier 0xBFB40000

Operands

  • 1: immediate
    Literal value encoded in the instruction. Written 0 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction. The ping is ignored if the waves are not sleeping. This allows for efficient polling on a memory location. The waves which are polling can sit in a long S_SLEEP between memory reads, but the wave which writes the value can tell them all to wake up early now that the data is available. This method is also safe from races since any waves that miss the ping resume when they complete their S_SLEEP. If the wave executing S_WAKEUP is in a threadgroup (in_tg set), then it wakes up all waves associated with the same threadgroup ID. Otherwise, S_WAKEUP is treated as an S_NOP.

Example

s_wakeup 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopp.s). Not from an AMD document, and not authored here.

Sources