s_delay_alu GPU Native ISA AMD Scalar

Branch & Control

s_delay_alu

Insert delay between dependent SALU/VALU instructions.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0000111
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 7 in OP rebuilds 0xBF870000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPP
Width 32 bits
Opcode 7
Identifier 0xBF870000

Operands

  • SIMM16
    Read. Specify one or more delay conditions to apply to the next VALU instructions in the instruction stream. Data format: 16 bits of arbitrary data. (OPR_DELAY, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_delay_alu 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources