s_set_inst_prefetch_distance GPU Native ISA AMD Scalar

Branch & Control

s_set_inst_prefetch_distance

Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch.

Also written as s_inst_prefetch. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 3.5)
101111111
31:23
0000100
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD RDNA 3.5). Opcode 4 in OP rebuilds 0xBF840000, an identifier AMD lists for this encoding. The same in AMD RDNA 3.

Format SOPP
Width 32 bits
Opcode 4
Identifier 0xBF840000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD RDNA 3.5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Example

s_set_inst_prefetch_distance 0xc1d1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources