s_nop GPU Native ISA AMD Scalar

Branch & Control

s_nop

Do nothing.

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0000000
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 0 in OP rebuilds 0xBF800000, an identifier AMD lists for this encoding. The same in the other 9 generations that define it.

Format SOPP
Width 32 bits
Opcode 0
Identifier 0xBF800000

Operands

  • SIMM16
    Read. 16-bit integer constant. Data format: 16 bits of arbitrary data. (OPR_SIMM16, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Examples: s_nop 0 // Wait 1 cycle. s_nop 0xf // Wait 16 cycles.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Description

Do nothing. Delay issue of next instruction by a small, fixed amount. Insert 0..15 wait states based on SIMM16[3:0]. 0x0 means the next instruction can issue on the next clock, 0xf means the next instruction can issue 16 clocks later.

Semantics

for i in 0U : SIMM16.u16[3 : 0].u32 do nop() endfor

Example

s_nop 0x0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources