s_nop GPU Native ISA AMD Scalar
S NOP Branch & Control
s_nop
Do nothing.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPP)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Examples: s_nop 0 // Wait 1 cycle. s_nop 0xf // Wait 16 cycles.
Related
More in Branch & Control
Reference
AMDGPU / GFX ISA
Description
Do nothing. Delay issue of next instruction by a small, fixed amount. Insert 0..15 wait states based on SIMM16[3:0]. 0x0 means the next instruction can issue on the next clock, 0xf means the next instruction can issue 16 clocks later.
Semantics
for i in 0U : SIMM16.u16[3 : 0].u32 do
nop()
endfor
Example
s_nop 0x0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 138. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project