s_set_vgpr_msb GPU Native ISA AMD Scalar

Branch & Control

s_set_vgpr_msb

AMDGPU SOPP scalar instruction. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Encoding

Binary Layout (AMD CDNA 5)
101111111
31:23
0000110
22:16
SIMM16
15:0
 

The ENC_SOPP layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 6 in OP rebuilds 0xBF860000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOPP
Width 32 bits
Opcode 6
Identifier 0xBF860000

Operands

  • SIMM16
    Read. SET_VGPR_MSB operand specifying MSBs for VGPR accesses. Data format: 16 bits of arbitrary data. (OPR_SET_VGPR_MSB, FMT_NUM_B16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPP encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Branch & Control

Reference

AMDGPU / GFX ISA

Sources