trap GPU Virtual ISA NVIDIA

trap Miscellaneous Instructions

trap;

Abort execution and generate an interrupt to the host CPU.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
trap; sm_10 Abort execution and generate an interrupt to the host CPU.

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Trap ↗
equivalent with restrictions
s_trap (AMDGPU)

Related

More in Miscellaneous Instructions

Reference

NVIDIA PTX ISA

Examples

trap;
@p  trap;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources