setmaxnreg GPU Virtual ISA NVIDIA

setmaxnreg Miscellaneous Instructions

setmaxnreg.action.sync.aligned.u32 imm-reg-count;

setmaxnreg provides a hint to the system to update the maximum number of per-thread registers owned by the executing warp to the value specified by the imm-reg-count operand.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 8.0
Minimum Target sm_90a

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
setmaxnreg.action.sync.aligned.u32 imm-reg-count; sm_90a setmaxnreg provides a hint to the system to update the maximum number of per-thread registers owned by the executing warp to the value specified by the imm-reg-count operand. Qualifier. (see the official PTX ISA docs for the full description)

Operands

  • imm-reg-count
    Operand

At a Glance

Data Types -

Related

More in Miscellaneous Instructions

Reference

NVIDIA PTX ISA

Description

setmaxnreg provides a hint to the system to update the maximum number of per-thread registers owned by the executing warp to the value specified by the imm-reg-count operand. Qualifier.dec is used to release extra registers such that the absolute per-thread maximum register count is reduced from its current value to imm-reg-count. Qualifier.inc is used to request additional registers such that the absolute per-thread maximum register count is increased from its current value to imm-reg-count. A pool of available registers is maintained per-CTA. (see the official PTX ISA docs for the full description)

Examples

setmaxnreg.dec.sync.aligned.u32 64;
setmaxnreg.inc.sync.aligned.u32 192;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources