bra GPU Virtual ISA NVIDIA

bra Control Flow Instructions

@p bra{.uni} tgt; // tgt is a label

Continue execution at the target.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
@p bra{.uni} tgt; // tgt is a label sm_10 Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, i.e. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Branch ↗
equivalent with restrictions
s_branch (AMDGPU)
s_cbranch_scc1 (AMDGPU)

Related

More in Control Flow Instructions

Reference

NVIDIA PTX ISA

Description

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, i.e. all active threads in a warp that are currently executing this instruction have identical values for the guard predicate and branch target.

Semantics

if (p) { pc = tgt; }

Examples

bra.uni  L_exit;    // uniform unconditional jump
@q  bra      L23;   // conditional branch

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources