ret GPU Virtual ISA NVIDIA

ret Control Flow Instructions

ret{.uni};

Return execution to caller’s environment.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 1.0
Minimum Target sm_10

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
ret{.uni}; sm_10 Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related AMDGPU Concepts

Function Return ↗
equivalent with restrictions
s_setpc_b64 (AMDGPU)

Related

More in Control Flow Instructions

Reference

NVIDIA PTX ISA

Description

Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the.uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution.

Examples

ret;
@p  ret;

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources