brx.idx GPU Virtual ISA NVIDIA

brx.idx Control Flow Instructions

@p brx.idx{.uni} index, tlist;

Index into a list of possible destination labels, and continue execution from the chosen label.

Encoding

PTX is a virtual instruction set. It has no single, stable native binary encoding - the compiler lowers this instruction to different native machine code depending on the selected NVIDIA target architecture (compute capability). This page intentionally shows no bit-diagram; see the target/version requirements below for what governs how this instruction compiles.
PTX ISA Version Introduced PTX ISA 6.0
Minimum Target sm_30

Syntax Forms

One mnemonic covers many type / state-space / scope / modifier combinations - each row below is an independently valid form.

Syntax Data Types State Space(s) Modifiers Min. Target Description
@p brx.idx{.uni} index, tlist; sm_30 Index into a list of possible destination labels, and continue execution from the chosen label. Conditional branches are specified by using a guard predicate. brx.idx. (see the official PTX ISA docs for the full description)

Operands

At a Glance

Data Types -

Related

More in Control Flow Instructions

Reference

NVIDIA PTX ISA

Description

Index into a list of possible destination labels, and continue execution from the chosen label. Conditional branches are specified by using a guard predicate. brx.idx.uni guarantees that the branch is non-divergent, i.e. all active threads in a warp that are currently executing this instruction have identical values for the guard predicate and the index argument. The index operand is a.u32 register. The tlist operand must be the label of a.branchtargets directive. It is accessed as a zero-based sequence using index. (see the official PTX ISA docs for the full description)

Semantics

if (p) { if (index < length(tlist)) { pc = tlist[index]; } else { pc = undefined; } }

Examples

.function foo () {
    .reg .u32 %r0;
    ...
    L1:
    ...
    L2:
// (truncated - see the official PTX ISA docs for the full example)

Reproduced from NVIDIA's official PTX ISA documentation for technical accuracy.

Sources