Branch Control Flow
Transfer control to a target instruction, optionally guarded by a predicate.
Vendor-Neutral Definition
PC = target if (no guard predicate, or guard predicate is true), else PC = PC + instruction_width.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both transfer control to a target address, optionally guarded by a condition.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | bra | s_branch, s_cbranch_scc1 |
| ISA Layer | Virtual | Native |
| Data Types | - | - |
| Version / Target Introduced | PTX ISA 1.0 | gfx942/gfx1100, gfx942/gfx1100 |
Important Differences
- AMDGPU has many distinct conditional-branch mnemonics gated on different scalar condition sources (s_cbranch_scc0/scc1, s_cbranch_vccz/vccnz, s_cbranch_execz/execnz, ...) rather than one generic guarded branch with an arbitrary predicate register the way PTX's @p bra is expressed.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ - LLVM Project
Verification method: documentation