AMDGPU / GFX Instructions GPU Native ISA AMD
2442 instructions - showing 100 per page, page 14 of 25 - AMDGPU/GFX is AMD's native, low-level
GPU instruction set family, assembled directly with no virtual intermediate layer. Supported
instructions and their exact encodings vary by GFX compatibility target (e.g.
gfx942, gfx1100). Scalar instructions execute once per wavefront on
the Scalar ALU; vector instructions execute per-lane on the Vector ALU, gated by the EXEC mask.
How AMDGPU compares to the other GPU ISA
Decode a AMDGPU instruction word
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| Mnemonic | Syntax | Format | GFX Targets | Unit | Summary |
|---|---|---|---|---|---|
| v_add_i32 | v_add_i32 | VOP2 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_lshl_u32 | v_add_lshl_u32 | VOP3 | gfx1100 | Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then… | |
| v_add_max_i32 | v_add_max_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_max_u32 | v_add_max_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_min_i32 | v_add_min_i32 | VOP3 | AMDGPU VOP3 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_min_u32 | v_add_min_u32 | VOP3 | AMDGPU VOP3 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_nc_i16 | v_add_nc_i16 | VOP3 | gfx1100 | Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_i32 | v_add_nc_i32 | VOP3 | gfx1100 | Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_u16 | v_add_nc_u16 | VOP3 | gfx1100 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | |
| v_add_nc_u32 | v_add_nc_u32 | VOP2 | Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_nc_u64 | v_add_nc_u64 | VOP2 | AMDGPU VOP2 vector instruction operating on u64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_add_u16 | v_add_u16 | VOP2 | Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. | ||
| v_add_u32 | v_add_u32 VDST, S0, S1 | VOP2 | gfx942, gfx1100 | Vector ALU | Per-lane add of two 32-bit unsigned vector operands. |
| v_addc_co_u32 | v_addc_co_u32 | VOP2 | Add two unsigned 32-bit integer inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a… | ||
| v_addc_u32 | v_addc_u32 | VOP2 | AMDGPU VOP2 vector instruction operating on u32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbit_b32 | v_alignbit_b32 | VOP3 | gfx1100 | Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector… | |
| v_alignbit_b32_opsel | v_alignbit_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32 | v_alignbyte_b32 | VOP3 | gfx1100 | Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector… | |
| v_alignbyte_b32_fake16 | v_alignbyte_b32_fake16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32_opsel | v_alignbyte_b32_opsel | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_alignbyte_b32_t16 | v_alignbyte_b32_t16 | VOP3 | AMDGPU VOP3 vector instruction operating on b32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b16 | v_and_b16 | VOP3 | gfx1100 | Calculate bitwise AND on two vector inputs and store the result into a vector register. | |
| v_and_b16_fake16 | v_and_b16_fake16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b16_t16 | v_and_b16_t16 | VOP2 | AMDGPU VOP2 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_and_b32 | v_and_b32 | VOP2 | gfx1100 | Calculate bitwise AND on two vector inputs and store the result into a vector register. | |
| v_and_or_b32 | v_and_or_b32 | VOP3 | gfx1100 | Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store… | |
| v_ashr_i32 | v_ashr_i32 | VOP2 | AMDGPU VOP2 vector instruction operating on i32 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_ashr_i64 | v_ashr_i64 | VOP3 | AMDGPU VOP3 vector instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_ashr_pk_i8_i32 | v_ashr_pk_i8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… | ||
| v_ashr_pk_u8_i32 | v_ashr_pk_u8_i32 | VOP3 | Given two signed 32-bit integers and a shift count, calculate the arithmetic shift right (preserving sign bit) of the two integers, saturate the two… | ||
| v_ashrrev_i16 | v_ashrrev_i16 | VOP2 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_ashrrev_i32 | v_ashrrev_i32 | VOP2 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_ashrrev_i64 | v_ashrrev_i64 | VOP3 | gfx1100 | Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the… | |
| v_bcnt_u32_b32 | v_bcnt_u32_b32 VDST, S0, S1 | VOP3 | gfx942, gfx1100 | Vector ALU | Per-lane accumulating population count. |
| v_bfe_i32 | v_bfe_i32 | VOP3 | gfx1100 | Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a… | |
| v_bfe_u32 | v_bfe_u32 | VOP3 | gfx1100 | Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into… | |
| v_bfi_b32 | v_bfi_b32 | VOP3 | gfx1100 | Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector… | |
| v_bfm_b32 | v_bfm_b32 | VOP2 | gfx1100 | Calculate a bitfield mask given a field offset and size and store the result into a vector register. | |
| v_bfrev_b32 | v_bfrev_b32 | VOP1 | gfx1100 | Reverse the order of bits in a vector input and store the result into a vector register. | |
| v_bitop3_b16 | v_bitop3_b16 | VOP3 | Calculate the generic bitwise operation of three 16-bit vector inputs using a truth table encoded in the instruction and store the result into a… | ||
| v_bitop3_b16_gfx1250 | v_bitop3_b16_gfx1250 | VOP3 | AMDGPU VOP3 vector instruction operating on b16 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.) | ||
| v_bitop3_b32 | v_bitop3_b32 | VOP3 | Calculate the generic bitwise operation of three 32-bit vector inputs using a truth table encoded in the instruction and store the result into a… | ||
| v_ceil_f16 | v_ceil_f16 | VOP1 | Round the half-precision float input up to next integer and store the result in floating point format into a vector register. | ||
| v_ceil_f32 | v_ceil_f32 | VOP1 | gfx1100 | Round the single-precision float input up to next integer and store the result in floating point format into a vector register. | |
| v_ceil_f64 | v_ceil_f64 | VOP1 | gfx1100 | Round the double-precision float input up to next integer and store the result in floating point format into a vector register. | |
| v_clrexcp | v_clrexcp | VOP1 | Clear this wave's exception state in the vector ALU. | ||
| v_cmp_class_f16 | v_cmp_class_f16 | VOPC | gfx1100 | Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the… | |
| v_cmp_class_f32 | v_cmp_class_f32 | VOPC | gfx1100 | Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the… | |
| v_cmp_class_f64 | v_cmp_class_f64 | VOPC | gfx1100 | Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the… | |
| v_cmp_eq_f16 | v_cmp_eq_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_f32 | v_cmp_eq_f32 VCC, S0, S1 | VOPC | gfx942, gfx1100 | Vector ALU | Per-lane single-precision equality compare, result written as an execution-mask-width bitmask. |
| v_cmp_eq_f64 | v_cmp_eq_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_i16 | v_cmp_eq_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_i32 | v_cmp_eq_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_i64 | v_cmp_eq_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_u16 | v_cmp_eq_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_u32 | v_cmp_eq_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_eq_u64 | v_cmp_eq_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_f_f16 | v_cmp_f_f16 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_f32 | v_cmp_f_f32 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_f64 | v_cmp_f_f64 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_i16 | v_cmp_f_i16 | VOPC | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | ||
| v_cmp_f_i32 | v_cmp_f_i32 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_i64 | v_cmp_f_i64 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_u16 | v_cmp_f_u16 | VOPC | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | ||
| v_cmp_f_u32 | v_cmp_f_u32 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_f_u64 | v_cmp_f_u64 | VOPC | gfx1100 | Set the per-lane condition code to 0. Store the result into VCC or a scalar register. | |
| v_cmp_ge_f16 | v_cmp_ge_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_f32 | v_cmp_ge_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_f64 | v_cmp_ge_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_i16 | v_cmp_ge_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_i32 | v_cmp_ge_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_i64 | v_cmp_ge_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_u16 | v_cmp_ge_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_u32 | v_cmp_ge_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_ge_u64 | v_cmp_ge_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_f16 | v_cmp_gt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_f32 | v_cmp_gt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_f64 | v_cmp_gt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_i16 | v_cmp_gt_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_i32 | v_cmp_gt_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_i64 | v_cmp_gt_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_u16 | v_cmp_gt_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_u32 | v_cmp_gt_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_gt_u64 | v_cmp_gt_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_f16 | v_cmp_le_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_f32 | v_cmp_le_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_f64 | v_cmp_le_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_i16 | v_cmp_le_i16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_i32 | v_cmp_le_i32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_i64 | v_cmp_le_i64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_u16 | v_cmp_le_u16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_u32 | v_cmp_le_u32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_le_u64 | v_cmp_le_u64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lg_f16 | v_cmp_lg_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmp_lg_f32 | v_cmp_lg_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmp_lg_f64 | v_cmp_lg_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than or greater than the second input. | |
| v_cmp_lt_f16 | v_cmp_lt_f16 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_f32 | v_cmp_lt_f32 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. | |
| v_cmp_lt_f64 | v_cmp_lt_f64 | VOPC | gfx1100 | Set the per-lane condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. |
Source
Normalized from AMD's official ROCm documentation, with the LLVM AMDGPU backend documentation as supplementary compiler-target information. ROCm documentation ↗