v_cmp_f_f32 GPU Native ISA AMD Vector

Comparison

v_cmp_f_f32

Set the per-lane condition code to 0. Store the result into VCC or a scalar register.

Encoding

Binary Layout (AMD CDNA 4)
0111110
31:25
01000000
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 64 in OP rebuilds 0x7C800000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 16), AMD RDNA 3 (opcode 16), AMD RDNA 2 (opcode 0), AMD RDNA 1 (opcode 0). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOPC
Width 32 bits
Opcode 64
Identifier 0x7C800000

Operands

  • vcc
    Written. Written in the assembly; this encoding has no field for it. N/A Data format: N/A (OPR_VCC, FMT_NUM_M64)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_F32)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOPC encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Semantics

D0.u64[laneId] = 1'0U; // D0 = VCC in VOPC encoding.

Example

v_cmp_f_f32 vcc, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources