v_cmp_eq_f32 GPU Native ISA AMD Vector

V CMP EQ F32 Comparison

v_cmp_eq_f32 VCC, S0, S1

Per-lane single-precision equality compare, result written as an execution-mask-width bitmask.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOPC) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOPC
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR, VCC

Operands

  • VCC
    Destination mask (VCC, or an arbitrary SGPR pair for the _e64 encoding)
  • S0
    First source
  • S1
    Second source

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Compare ↗
equivalent with restrictions
setp (PTX)

Reference

AMDGPU / GFX ISA

Semantics

VCC[lane] = (S0[lane].f32 == S1[lane].f32) for each active lane; VCC is 32 bits wide in wave32 mode, 64 bits in wave64 mode.

Sources