v_cmp_eq_f32 GPU Native ISA AMD Vector

Comparison

v_cmp_eq_f32 VCC, S0, S1

Per-lane single-precision equality compare, result written as an execution-mask-width bitmask.

Encoding

Binary Layout (AMD CDNA 5)
0111110
31:25
00010010
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 18 in OP rebuilds 0x7C240000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 66), AMD CDNA 3 (opcode 66), AMD CDNA 2 (opcode 66), AMD CDNA 1 (opcode 66), AMD RDNA 2 (opcode 2), AMD RDNA 1 (opcode 2). The same in AMD RDNA 4, AMD RDNA 3.5, AMD RDNA 3.

Format VOPC
Width 32 bits
Opcode 18
Identifier 0x7C240000
Execution Unit Vector ALU
Register Classes VGPR, VCC

Operands

  • VCC
    Destination mask (VCC, or an arbitrary SGPR pair for the _e64 encoding)
  • S0
    First source
  • S1
    Second source

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Compare ↗
equivalent with restrictions
setp (PTX)

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Set the per-lane condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register.

Semantics

VCC[lane] = (S0[lane].f32 == S1[lane].f32) for each active lane; VCC is 32 bits wide in wave32 mode, 64 bits in wave64 mode.

Example

v_cmp_eq_f32  vcc, v0, v1   // vcc[lane] = (v0[lane] == v1[lane])

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources