s_setvskip GPU Native ISA AMD Scalar

Comparison

s_setvskip

Enables or disables VSKIP mode.

Encoding

Binary Layout (AMD CDNA 4)
101111110
31:23
0010000
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 16 in OP rebuilds 0xBF100000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format SOPC
Width 32 bits
Opcode 16
Identifier 0xBF100000

Operands

  • SSRC0
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U32)
  • SSRC1
    Read. N/A Data format: N/A (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPC encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Description

Enables or disables VSKIP mode. When VSKIP is enabled, no VOP*/M*BUF/MIMG/DS/FLAT instructions are issued. Note that VSKIPped memory instructions do not manipulate the waitcnt counters; as a result, if there are outstanding memory requests the shader may want to issue S_WAITCNT 0 prior to enabling VSKIP, otherwise the shader must be careful not to count VSKIPped instructions in waitcnt calculations.

Semantics

VSKIP = S0.u32[S1.u32[4 : 0]]

Example

s_setvskip 1, 0     // Enable vskip mode.
s_setvskip 0, 0     // Disable vskip mode.

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources