s_cmp_lg_u32 GPU Native ISA AMD Scalar

Comparison

s_cmp_lg_u32

Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input.

Encoding

Binary Layout (AMD CDNA 5)
101111110
31:23
0000111
22:16
SSRC1
15:8
SSRC0
7:0
 

The ENC_SOPC layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 7 in OP rebuilds 0xBF070000, an identifier AMD lists for this encoding. The same in the other 9 generations that define it.

Format SOPC
Width 32 bits
Opcode 7
Identifier 0xBF070000

Operands

  • SSRC0
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)
  • SSRC1
    Read. All scalar operands. Covers all operands that are allowed as scalar sources. Data format: Unsigned 32-bit integral data. (OPR_SSRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPC encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Note that S_CMP_LG_I32 and S_CMP_LG_U32 are identical opcodes, but both are provided for symmetry.

Related

More in Comparison

Reference

AMDGPU / GFX ISA

Semantics

SCC = S0.u32 <> S1.u32

Example

s_cmp_lg_u32 s0, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources