s_cmp_gt_i32 GPU Native ISA AMD Scalar
S CMP GT I32 Comparison
s_cmp_gt_i32
Set SCC to 1 iff the first scalar input is greater than the second scalar input.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOPC)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Comparison
Reference
AMDGPU / GFX ISA
Semantics
SCC = S0.i32 > S1.i32
Example
s_cmp_gt_i32 s0, 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 133. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project